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<section-title-en>2.2 Computational Model</section-title-en>
<section-title-ch>2.2 计算模型</section-title-ch>
<p-en>
	This section pieces together a highly simplified model for a computer that implements the Intel architecture, illustrated in Figure 4. This simplified model is intended to help the reader's intuition process the fundamental concepts used by the rest of the paper. The following sections gradually refine the simplified model into a detailed description of the Intel architecture.
</p-en>
<p-ch>
	本节拼凑出一个实现英特尔架构的计算机的高度简化模型，如图4所示。这个简化模型的目的是帮助读者直观地处理本文其他部分所使用的基本概念。下面的章节将逐步把简化模型细化为对英特尔架构的详细描述。
</p-ch>
<img src="fig.4.jpg" />
<p-en>
	Figure 4: A computer's core is its processors and memory, which are connected by a system bus. Computers also have I/O devices, such as keyboards, which are also connected to the processor via the system bus.
</p-en>
<p-ch>
	图4：计算机的核心是它的处理器和内存，它们通过系统总线连接。计算机还有键盘等I/O设备，这些设备也通过系统总线与处理器相连。
</p-ch>
<p-en>
	The building blocks for the model presented here come from [165], which introduces the key abstractions in a computer system, and then focuses on the techniques used to build software systems on top of these abstractions
</p-en>
<p-ch>
	这里介绍的模型的构件来自[165]，它介绍了计算机系统中的关键抽象，然后重点介绍了在这些抽象之上构建软件系统的技术。
</p-ch>
<p-en>
	The memory is an array of storage cells, addressed using natural numbers starting from 0, and implements the abstraction depicted in Figure 5. Its salient feature is that the result of reading a memory cell at an address must equal the most recent value written to that memory cell.
</p-en>
<p-ch>
	存储器是一个存储单元的数组，使用从0开始的自然数寻址，实现了图5所描述的抽象。它的突出特点是，在某一地址读取一个存储单元的结果必须等于最近写入该存储单元的值。
</p-ch>
<img src="fig.5.jpg" />
<p-en>Figure 5: The memory abstraction</p-en>
<p-ch>图5：内存抽象</p-ch>
<p-en>
	A logical processor repeatedly reads instructions from the computer's memory and executes them, according to the flowchart in Figure 6.
</p-en>
<p-ch>
	逻辑处理器根据图6的流程图，反复从计算机内存中读取指令并执行。
</p-ch>
<img src="fig.6.jpg" />
<p-en>Figure 6: A processor fetches instructions from the memory and executes them. The RIP register holds the address of the instruction to be executed.</p-en>
<p-ch>图6：处理器从内存中获取指令并执行。RIP寄存器保存着要执行的指令的地址。</p-ch>
<p-en>
	The processor has an internal memory, referred to as the register file. The register file consists of Static Random Access Memory (SRAM) cells, generally known as registers, which are significantly faster than DRAM cells, but also a lot more expensive.
</p-en>
<p-ch>
	处理器有一个内部存储器，称为寄存器文件。寄存器文件由静态随机存取存储器(SRAM)单元组成，一般称为寄存器，它比DRAM单元快得多，但价格也贵得多。
</p-ch>
<p-en>
	An instruction performs a simple computation on its inputs and stores the result in an output location. The processor's registers make up an execution context that provides the inputs and stores the outputs for most instructions. For example, ADD RDX, RAX, RBX performs an integer addition, where the inputs are the registers RAX and RBX, and the result is stored in the output register RDX.
</p-en>
<p-ch>
	指令对其输入进行简单的计算，并将结果存储在输出位置。处理器的寄存器构成了一个执行上下文，为大多数指令提供输入并存储输出。例如，ADD RDX，RAX，RBX执行一个整数加法，其中输入是寄存器RAX和RBX，结果存储在输出寄存器RDX中。
</p-ch>
<p-en>
	The registers mentioned in Figure 6 are the instruction pointer (RIP), which stores the memory address of the next instruction to be executed by the processor, and the stack pointer (RSP), which stores the memory address of the topmost element in the call stack used by the processor's procedural programming support. The other execution context registers are described in §2.4 and §2.6.
</p-en>
<p-ch>
	图6中提到的寄存器是指令指针(RIP)和堆栈指针(RSP)，前者存储了处理器要执行的下一条指令的内存地址，后者存储了处理器的过程式编程支持所使用的调用堆栈中最上面元素的内存地址。其他执行上下文寄存器在×2.4和×2.6中介绍。
</p-ch>
<p-en>
	Under normal circumstances, the processor repeatedly reads an instruction from the memory address stored in RIP, executes the instruction, and updates RIP to point to the following instruction. Unlike many RISC architectures, the Intel architecture uses a variable-size instruction encoding, so the size of an instruction is not known until the instruction has been read from memory.
</p-en>
<p-ch>
	在正常情况下，处理器会反复从RIP中存储的内存地址中读取一条指令，执行该指令，并更新RIP指向下一条指令。与许多RISC架构不同的是，Intel架构采用的是可变大小的指令编码，因此在从内存中读取指令之前，并不知道指令的大小。
</p-ch>
<p-en>
	While executing an instruction, the processor may encounter a fault, which is a situation where the instruction's preconditions are not met. When a fault occurs, the instruction does not store a result in the output location. Instead, the instruction's result is considered to be the fault that occurred. For example, an integer division instruction DIV where the divisor is zero results in a Division Fault (#DIV).
</p-en>
<p-ch>
	在执行指令时，处理器可能会遇到故障，即指令的先决条件没有得到满足的情况。当发生故障时，指令不会在输出位置存储结果。相反，指令的结果被认为是发生的故障。例如，整数除法指令DIV，其中除数为零，结果为除法故障（#DIV）。
</p-ch>
<p-en>
	When an instruction results in a fault, the processor stops its normal execution flow, and performs the fault handler process documented in §2.8.2. In a nutshell, the processor first looks up the address of the code that will handle the fault, based on the fault's nature, and sets up the execution environment in preparation to execute the fault handler.
</p-en>
<p-ch>
	当一条指令导致故障时，处理器会停止正常的执行流程，并执行§2.8.2中记载的故障处理程序。简而言之，处理器首先根据故障性质查找处理故障的代码地址，并设置执行环境，准备执行故障处理程序。
</p-ch>
<p-en>
	The processors are connected to each other and to the memory via a system bus, which is a broadcast network that implements the abstraction in Figure 7.
</p-en>
<p-ch>
	处理器之间和存储器之间通过系统总线连接，系统总线是一个广播网络，实现了图7的抽象。
</p-ch>
<img src="fig.7.jpg" />
<p-en>Figure 7: The system bus abstraction</p-en>
<p-ch>图7：系统总线抽象</p-ch>
<p-en>
	During each clock cycle, at most one of the devices connected to the system bus can send a message, which is received by all the other devices connected to the bus. Each device attached to the bus decodes the operation codes and addresses of all the messages sent on the bus and ignores the messages that do not require its involvement.
</p-en>
<p-ch>
	在每个时钟周期内，连接到系统总线上的设备中最多有一个设备可以发送消息，所有连接到总线上的其他设备都会收到该消息。连接到总线上的每个设备都会对总线上发送的所有消息的操作码和地址进行解码，并忽略不需要它参与的消息。
</p-ch>
<p-en>
	For example, when the processor wishes to read a memory location, it sends a message with the operation code READ-REQUEST and the bus address corresponding to the desired memory location. The memory sees the message on the bus and performs the READ operation. At a later time, the memory responds by sending a message with the operation code READ-RESPONSE, the same address as the request, and the data value set to the result of the READ operation.
</p-en>
<p-ch>
	例如，当处理器希望读取一个存储器位置时，它发送一个带有操作代码READ-REQUEST和所需存储器位置对应的总线地址的消息。存储器在总线上看到该消息并执行READ操作。在稍后的时间，存储器通过发送带有操作代码READ-RESPONSE、与请求相同的地址以及设置为READ操作结果的数据值的消息作出响应。
</p-ch>
<p-en>
	The computer communicates with the outside world via I/O devices, such as keyboards, displays, and network cards, which are connected to the system bus. Devices mostly respond to requests issued by the processor. However, devices also have the ability to issue interrupt requests that notify the processor of outside events, such as the user pressing a key on a keyboard.
</p-en>
<p-ch>
	计算机通过与系统总线相连的键盘、显示器、网卡等I/O设备与外界通信。设备主要响应处理器发出的请求。但是，设备也能够发出中断请求，通知处理器外界事件，如用户按下键盘上的某个键。
</p-ch>
<p-en>
	Interrupt triggering is discussed in §2.12. On modern systems, devices send interrupt requests by issuing writes to special bus addresses. Interrupts are considered to be hardware exceptions, just like faults, and are handled in a similar manner.
</p-en>
<p-ch>
	中断触发将在§2.12中讨论。在现代系统中，设备通过向特殊总线地址发出写入来发送中断请求。中断被认为是硬件异常，就像故障一样，并以类似的方式处理。
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